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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM 200pin One Bank Unbuffered DDR SO-DIMM Based on DDR266/200 32Mx8 SDRAM Features
* JEDEC Standard 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) DDR SDRAM. * Performance : * 32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8
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* Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge
PC1600 - 8B 2 100 10 200
PC2100 - 75B 2.5 133 7.5 266 - 7K 2 133 7.5 266 MHz ns MHz Unit
* Programmable Operation: - DIMM CAS Latency: 2, 2.5 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write
Speed Sort DIMM CAS Latency
f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency
* Auto Refresh (CBR) and Self Refresh Modes * 13/10/2 Addressing (row/column/bank) * Serial Presence Detect * Gold contacts
* Intended for 100 MHz and 133 MHz applications * Inputs and outputs are SSTL-2 compatible * VDD = 2.5Volt 0.2, VDDQ = 2.5Volt 0.2 * Single Pulsed RAS interface * SDRAMs have 4 internal banks for concurrent operation * Module has one physical bank * Differential clock inputs
* Automatic and controlled precharge commands * 7.8 s Max. Average Periodic Refresh Interval
* SDRAMs in 66-pin TSOP Type II Package
Description
NT256D64S88A2GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all devices on the DIMM.
Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The last 128 bytes are available to the customer. All NANYA 200pin DDR SO-DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint.
Ordering Information
Part Number NT256D64S88A2GM-7K 133MHz (7.5ns @ CL= 2 ) 133MHz (7.5ns @ CL= 2.5 ) NT256D64S88A2GM-75B 100MHz (10ns @ CL = 2 ) 125MHz (8ns @ CL = 2.5 ) NT256D64S88A2GM-8B 100MHz (10ns @ CL = 2 ) PC1600 PC2100 32Mx64 Gold Speed 143MHz (7ns @ CL = 2.5 ) PC2100 Organization Leads Power
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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(c) NANYA TECHNOLOGY CORP.
NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Pin Description
CK0, CK1,
CK0 , CK1
CKE0,CKE1
Differential Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag.
DQ0-DQ63 DQS0-DQS7 DM0-DM7 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD
Data input/output Bidirectional data strobes Data Masks Power (2.5V) Supply voltage for DQs(2.5V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply(2.5V)
RAS CAS
WE
S0
A0-A9, A11,A12 A10/AP BA0, BA1 VREF VDDID
Pinout
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Front VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC DU VSS NC NC VDD CKE1 NC NC Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Back VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC DU VSS VSS VDD VDD CKE0 DU A11 Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Front A9 VSS A7 A5 A3 A1 VDD A10/AP VDD Pin 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Back A8 VSS A6 A4 A2 A0 VDD BA1 Pin 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back DQ46 DQ47 VDD
CK1
CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
RAS CAS
DU DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS
WE
S0
DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS
CK0
VSS DQ16 DQ17 VDD DQS2 DQ18
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Input/Output Functional Description
Symbol CK0 , CK1, CK2 Type (SSTL) Polarity Positive Edge Function The positive line of the differential pair of system clock inputs which drives the input to the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising edge of their associated clocks. on-DIMM PLL. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS , CAS , WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to A0 - A9 A10/AP A11,A12 (SSTL) invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63, DQS0 - DQS7 (SSTL) (SSTL) Active High Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. The data write masks, associated with one data byte. In Write mode, DM operates as a DM0 - DM7 Input Active High byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. VDD , VSS SA0 - SA2 SDA SCL V DDSPD Supply Supply Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply.
CK0 , CK1 , CK2
(SSTL)
Negative The negative line of the differential pair of system clock inputs which drives the input to the Edge Active High
CKE0
(SSTL)
S0
(SSTL)
Active Low Active Low
RAS , CAS , WE
VREF VDDQ BA0, BA1
(SSTL) Supply Supply (SSTL)
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Functional Block Diagram ( 1 Bank, 32Mx8 DDR SDRAMs )
S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0 BA0-BA1 A0-A12 RAS CAS CKE0 WE DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CK0 120 ohm CK0 CK1 120 ohm CK1 CK2 120 ohm CK2 VDDQ VDD VREF VSS VDDID D0 D0 D0 D0 D7 D7 D7 D7 SDRAM x 0 SDRAM x 4 SDRAM x 4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
DQS4 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
D0
D4
D1
D5
D2
D6
D3
D7
CS : SDRAMs D0 -D7 BA0 - BA1 : SDRAMs D0 -D7 A0 - A12: SDRAMs D0 -D7 RAS : SDRAMs D0 -D7 CAS : SDRAMs D0 -D7 CKE0 : SDRAMs D0 -D7 WE : SDRAMs D0 -D7 Serial PD
SCL WP
A0 SA0
A1 SA1
A2 SA2
SDA
Notes : 1. 2. 3. 4.
Strap: see Note 4
DQ-to-I/O wring may be changed within a byte. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ.
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Serial Presence Detect -- Part 1 of 2
SPD Entry Value Byte Description Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank Data Width of Assembly Data Width of Assembly (cont' ) Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time at CL=2.5 DDR SDRAM Device Access Time from Clock at CL=2.5 DIMM Configuration Type Refresh Rate/Type Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width DDR SDRAM Device Attr: Min CLk Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency DDR SDRAM Device Attributes: DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2 Maximum Data Access Time from Clock at CL=2 Minimum Clock Cycle Time at CL=1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time(tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved SPD Revision Checksum Data Initial 0.9ns 0.9ns 0.5ns 0.5ns 20ns 15ns 20ns 45ns 7.5ns 0.75ns 2/2.5 7ns 0.75ns DDR266A DDR266B -7K 0 1 2 3 4 5 6. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 -75B 128 256 SDRAM DDR 13 10 1 X64 X64 SSTL 2.5V 7.5ns 0.75ns Non-Parity SR/1x(7.8us) X8 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock +/-0.2V Voltage Tolerance 10ns 0.75ns N/A N/A 20ns 15ns 20ns 45ns 256MB 0.9ns 0.9ns 0.5ns 0.5ns Undefined Initial Initial 00 8F 1.1ns 1.1ns 0.6ns 0.6ns 90 90 50 50 20ns 15ns 20ns 50ns 50 3C 50 2D 10ns 0.8ns 75 75 2/2.5 0C 8ns 0.8ns 70 75 DDR200 -8B Serial PD Data Entry (Hexadecimal) DDR266A DDR266B -7K -75 80 08 07 0D 0A 01 40 00 04 75 75 00 82 08 00 01 0E 04 0C 01 02 20 00 A0 75 00 00 50 3C 50 2D 40 90 90 50 50 00 00 BF 00 45 B0 B0 60 60 50 3C 50 32 A0 80 0C 80 80 DDR200 -8B Note
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Serial Presence Detect -- Part 2 of 2
SPD Entry Value Byte 64-71 72 73-90 91-92 93-94 95-98 1. 2. Description Manufacturer' JEDED ID Code s Module Manufacturing Location Module Part number Module Revision Code Module Manufacturing Data Module Serial Number N/A DDR266A DDR266B -7K -75B NANYA N/A N/A N/A Year/Week Code Serial Number Undefined N/A 00 DDR200 -8B Serial PD Data Entry (Hexadecimal) DDR266A DDR266B -7K -75 7F7F7F0B00000000 00 00 00 yy/ww 00 00 1,2 00 DDR200 -8B Note
99-255 Reserved yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Absolute Maximum Ratings
Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Parameter Voltage on I/O pins relative to Vss Voltage on Input relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating -0.5 to VDDQ+0.5 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 0 to+70 -55 to +150 8 50 Units V V V V C C W mA
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter Input Capacitance: CK0, CK0 , CK1, CK1 , CK2, CK2 Input Capacitance: A0-A11, BA0, BA1, WE , RAS , CAS , CKE0, S0 Input Capacitance: SA0-SA2, SCL Input/Output Capacitance DQ0-63; DQS0-7 Symbol CI1 CI2 CI4 CIO1 Max. 12 30 9 7 Units pF pF pF pF Notes 1 1 1 1,2
CIO3 11 pF Input/Output Capacitance: SDA 1. VDDQ = VDD = 2.5V 0.2V, f = 100 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. 2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level.
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM DC Electrical Characteristics and Operating Conditions
( TA = 0 C ~ 70 C ; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol Parameter Supply Voltage I/O Supply Voltage Supply Voltage, I/O Supply Voltage /O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Leakage Current II Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current IOZ (DQs are disabled; 0V Vout VDDQ Output High Current IOH (VOUT = VDDQ -0.373V, min VREF , min VTT ) Output Low Current IOL (VOUT = 0.373, max VREF , max VTT ) 16.8 mA 1 -16.8 mA 1 -5 5 uA 1 -5 5 uA 1 Min 2.3 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.30 Max 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF- 0.15 VDDQ + 0.3 V DDQ + 0.6 Units V V V V V V V V V 1,2 1,3 1 1 1 1,4 Notes 1 1
VDD VDDQ
VSS , VSSQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC)
1. Inputs are not recognized as valid until V REF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF , and must track variations in the DC level of V REF . 4. VID is the magnitude of the difference between the input level on CK and the input level on CK .
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to V SS . 2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and I DD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level.
AC Output Load Circuits
VTT 50 ohms Output VOUT 30 pF Timing Reference Point
AC Operating Conditions
( TA = 0 C ~ 70 C ; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Parameter/Condition Input High (Logic 1) Voltage. Input Low (Logic 0) Voltage. Input Differential Voltage, CK and CK Inputs Input Differential Pair Cross Point Voltage, CK and CK Inputs 0.62 (0.5*VDDQ ) - 0.2 Min V REF + 0.31 V REF ? 0.31 V DDQ + 0.6 (0.5*VDDQ ) +? 0.2 Max Unit V V V V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4
1. Input slew rate = 1V/ ns . 2. Inputs are not recognized as valid until V REF stabilizes. 3. V ID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Operating, Standby, and Refresh Currents
( TA = 0 C ~ 70 C ; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol I DD0 Parameter/Condition Operating Current : one bank; active / precharge; tRC = tRC (MIN) ; tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current : one bank; active / read / precharge; Burst = 2; I DD1 tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA; address and control inputs changing once per clock cycle I DD2P I DD2N I DD3P Precharge Power-Down Standby Current : all banks idle; power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN) Idle Standby Current : CS VIH (MIN) ; all banks idle; CKE VIH(MIN) ; tCK = tCK (MIN) ; address and control inputs changing once per clock cycle Active Power-Down Standby Current : one bank active; power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN) Active Standby Current : one bank; active / precharge; CS VIH (MIN) ; I DD3N CKE VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current : one bank; Burst = 2; reads; continuous burst; I DD4R address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN) ; IOUT = 0mA Operating Current : one bank; Burst = 2; writes; continuous burst; I DD4W address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) I DD5 I DD6 Auto-Refresh Current : Self-Refresh Current : CKE ?.2V 0 t RC = t RFC (MIN) t RC = 7.8 s 1280 132 24 1360 132 24 mA mA mA 1,2 1,2,4 1,2,3 920 1200 mA 1,2 1040 1320 mA 1,2 400 480 mA 1,2 120 240 120 120 280 120 mA mA mA 1,2 1,2 1,2 720 880 mA 1,2 600 680 mA 1,2 PC1600 PC2100 Unit Notes
1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns . 3. Enables on-chip refresh and address counters. 4. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s.
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NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 C ~ 70 C ; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK tCH tCL tCK tCK tDH Parameter DQ output access time from CK/ CK DQS output access time from CK/ CK CK high-level width CK low-level width Clock cycle time CL=2.5 CL=2 -7K Min. -0.75 -0.75 0.45 0.45 7 7.5 0.5 Max. +0.75 +0.75 0.55 0.55 12 12 Min. -0.75 -0.75 0.45 0.45 7.5 10 0.5 -75B Max. +0.75 +0.75 0.55 0.55 12 12 Min. -0.8 -0.8 0.45 0.45 8 10 0.6 -8B Max. +0.8 +0.8 0.55 0.55 12 12 Unit ns ns tCK tCK ns ns ns Notes 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 ,15,16 1,2,3,4 ,15,16 1,2,3,4 1, 2, 3, 4, 5 1, 2, 3, 4, 5 1,2,3,4 1,2,3,4 1,2,3,4
DQ and DM input hold time
tDS tDIPW tHZ
DQ and DM input setup time DQ and DM input pulse width (each input) Data-out high-impedance time from CK/ CK Data-out low-impedance time from CK/ CK DQS-DQ skew (DQS & associated DQ signals) DQS-DQ skew (DQS & all DQ signals) Minimum half clk period for any given
0.5 1.75 -0.75 +0.75
0.5 1.75 -0.75 +0.75
0.6 2 -0.8 +0.8
ns ns ns
tLZ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
tDQSQ tDQSQA tHP
0.5 0.5 tCH or tCL tHP 0.75ns 0.75 0.35 0.2 0.2 14 0 1.25 tCH or tCL tHP 0.75ns 0.75 0.35 0.2 0.2 15 0
0.5 0.5 tCH or tCL tHP 1.0ns 1.25 0.75 0.35 0.2 0.2 16 0
0.6 0.6
ns ns tCK
cycle; defined by clk high(tCH ) or clk low (tCL ) time
tQH tDQSS tDQSL,H tDSS tDSH tMRD tWPRES
Data output hold time from DQS Write command to 1st DQS latching transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time
tCK 1.25 tCK tCK tCK tCK ns ns
1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1, 2, 3, 4, 7 1, 2, 3, 4, 6 1,2,3,4 2, 3, 4, 9, 11, 12 2, 3, 4,
tWPST tWPRE tIH
Write postamble Write preamble Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate)
0.40 0.25 0.9
0.60
0.40 0.25 1.1
0.60
0.40 0.25 1.1
0.60
tCK tCK ns
tIS
0.9
1.1
1.1
ns
9, 11, 12 2, 3, 4,
tIH
1.0
1.1
1.1
ns
10, 11, 12, 14
Preliminary 01 / 2002
11
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 C ~ 70 C ; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 2 of 2) Symbol Parameter Address and control input setup time tIS (slow slewrate) tIPW tRPRE tRPST tRAS tRC command period Auto-refresh to Active/Auto-refresh tRFC command period tRCD tRAP Autoprecharge tRP tRRD command tWR Write recovery time 15 (tWR/ tCK ) + (tRP/ tCK ) tWTR tXSNR command tXSRD tREFI Exit self-refresh to read command Average Periodic Refresh Interval 200 7.8 200 7.8 200 7.8 tCK s 1,2,3,4 1, 2, 3, 4, 8 Internal write to read command delay Exit self-refresh to non-read 75 75 80 ns 1,2,3,4 1 15 (tWR/ tCK ) + (tRP / tCK ) 1 15 (tWR/ tCK ) + (tRP / tCK ) 1 tCK 1,2,3,4 ns 1,2,3,4 Precharge command period Active bank A to Active bank B 15 15 15 ns 20 20 20 ns 1,2,3,4 1,2,3,4 Active to Read or Write delay Active to Read Command with 20 20 20 ns 20 20 20 ns 1,2,3,4 1,2,3,4 75 75 80 ns 1,2,3,4 Input pulse width Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh 65 65 70 ns 2.2 0.9 0.40 45 1.1 0.60 120,000 2.2 0.9 0.40 45 1.1 0.60 120,000 0.9 0.40 50 1.1 0.60 120,000 ns tCK tCK ns 1.0 1.0 1.1 ns -7K Min. Max. Min. -75B Max. Min. -8B Max. Unit Notes 2, 3, 4, 10, 11, 12, 14 2, 3, 4, 12 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4
Auto precharge write recovery + tDAL precharge time
1, 2, 3, tCK 4, 13
Preliminary 01 / 2002
12
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM AC Timing Specification Notes
1. Input slew rate = 1V/ns. 2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross: the input reference level for signals other than CK/ CK , is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT . 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS . 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/ CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns D ? elta ( tIS ) 0 +50 Delta ( tIH ) 0 0 Unit ps ps Note 1,2 1,2 1,2
0.3 V/ns +100 0 ps 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns Delta ( tDS ) 0 +75 Delta ( tDH ) 0 +75 Unit ps ps
Note 1,2 1,2
0.3 V/ns +150 +150 ps 1,2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. Delta Rise and Fall Rate 0.0 ns/V 0.25 ns/V Delta ( tDS ) 0 +50 Delta ( tDH ) 0 +50 Unit ps ps Note 1,2,3,4 1,2,3,4
0.5 ns/V +100 +100 ps 1,2,3,4 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
Preliminary 01 / 2002
13
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D64S88A2GM 256MB : 32M x 64 PC2100 / PC1600 Unbuffered DDR SO-DIMM Package Dimensions
FRONT
67.60 63.60
4.00
6.00
(2X) 1.80 2.15
1
39 11.40
41
199
Detail A 4.20 47.40 1.80
Detail B
2.45
BACK
Side
3.80 MAX
2
40
42
200
20.00
1.00+/- 0.10
Detail A 0.25 MAX
Detail B 0.45
4.00+/-0.10
Note : All dimensions are typical unless otherwise stated. Unit : Millimeters
Preliminary 01 / 2002
14
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
2.55
1.00+/- 0.1
0.60
31.75
(c) NANYA TECHNOLOGY CORP.

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